1. Bishnu Prasad Das, Bharadwaj Amrutur and Hidetoshi Onodera, “On-chip gate delay variability measurement in scaled technology node", in Book title: Nano-CMOS and Post-CMOS Electronics: Vol 2. Circuits and Design, Edited by S. P. Mohanty and A. Srivastava, The Institute of Engineering and Technology (IET), UK, 2015, ISBN: 978-1-84919-999-5.
Available : http://www.theiet.org/resources/books/circuits/Ncmosvol2.cfm
P5. Bishnu Prasad Das and Saragada Prasanna Kumar, “An In-memory computation (IMC)-based hardware accelerator system using a configurable digital-to-analog converter (DAC) and method capable of performing multi-bit multiply-and-accumulate (MAC) operations,” Dated 29/09/2023, Indian Patent Application No. 202311065832 (Filed)
P4. Bishnu Prasad Das and A. Verma , “Reconfigurable CORDIC Architecture with Non-Power-of-2 Angle Set of Microrotations and method Thereof” Dated 25/06/2026 and Indian patent number: 593463 (Granted)
P3. Bishnu Prasad Das and Saragada Prasanna Kumar, “A configurable SRAM-based In-memory Computation (IMC) Accelerator,” Dated: 17.04.2026 and Indian patent number: 587120 (Granted)
P2. Lawrence Pileggi, Bishnu P. Das, Kaushik Vaidyanathan, "Testing integrated circuits during split fabrication," Dated Nov 24, 2016 and US 2016/0341786 A1. (Granted)
P1. Bharadwaj Amrutur and Bishnu Prasad Das, "Gate Delay Measurement Circuit and Method of Determining a Delay of a Logic Gate," July 17, 2012 and US patent No. 8,224,604 B1. (Granted)
Journal Papers
J21. Aranya Gupta, Amit Surpur, Bishnu Prasad Das, and Sanjeev Manhas. 2025. A Unified Approach to a Secure and Lightweight Mutual Authentication Protocol Using Pre-Characterized COTS SRAM ICs for IoT Applications. ACM Trans. Embed. Comput. Syst. 24, 5, Article 81 (September 2025), 27 pages. https://doi.org/10.1145/3748328
J20. A. Verma, B. P. Das, P. N. Singh and K. Okada, "A Low-Jitter and Spur Dual-Edge Sub-Sampling Phase-Locked Loop With Double-Balanced Sampling Mixer-Adopted Phase Detector," in IEEE Transactions on Microwave Theory and Techniques, vol. 73, no. 11, pp. 8917-8928, Nov. 2025, doi: 10.1109/TMTT.2025.3592277
J19. A. Gupta, B. P. Das, S. Manhas, and R. Sadhukhan, "Weak PUF-Based Variable Latency Obfuscation Technique for ML-Attack Resilient Arbiter PUFs," in IEEE Embedded Systems Letters, doi: 10.1109/LES.2025.3592298.
J18. A. Verma and B. Prasad Das, "Light-Weight Low-Latency Reconfigurable CORDIC Architecture With a New Non-Power-of-2 Angle Set of Microrotations," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 72, no. 10, pp. 5861-5871, Oct. 2025, doi: 10.1109/TCSI.2025.3546823.
J17. P. Kumar Saragada and B. Prasad Das, "Process-Variation-Aware In-Memory Computation With Improved Linearity Using On-Chip Configurable Current-Steering Thermometric DAC," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 10, pp. 4586-4596, Oct. 2024, doi: 10.1109/TCSI.2024.3422883.
J16. P. Sharma and B. P. Das, "On-Chip Characterization of Ultra-Low Voltage Standard Cell Library Considering Input Slew and Output Capacitance," in IEEE Transactions on Electron Devices, vol. 71, no. 1, pp. 308-315, Jan. 2024, doi: 10.1109/TED.2023.3319598.
J15. A. Verma, K. Kiyawat, B. P. Das and P. K. Meher, "An Efficient Scaling-Free Folded Hyperbolic CORDIC Design Using a Novel Low-Complexity Power-of-2 Taylor Series Approximation," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 8, pp. 1167-1177, Aug. 2023, doi: 10.1109/TVLSI.2023.3281078.
J14. P. K. Saragada, S. Manna, A. Singh and B. P. Das, "A Configurable 10T SRAM-Based IMC Accelerator With Scaled-Voltage-Based Pulse Count Modulation for MAC and High-Throughput XAC," in IEEE Transactions on Nanotechnology, vol. 22, pp. 222-227, 2023, doi: 10.1109/TNANO.2023.3269946.
J13. P. K. Saragada and B. P. Das, "In-Memory Computation With Improved Linearity Using Adaptive Sparsity-Based Compact Thermometric Code," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 10, pp. 1473-1483, Oct. 2022, doi: 10.1109/TVLSI.2022.3199396.
J12. Bishnu Prasad Das, “On-chip static and dynamic monitors for low power applications” Springer CSI Transactions on ICT, June 2020, 8(2):123–127 https://doi.org/10.1007/s40012-020-00303
J11. P. Sharma and B. P. Das, "Design and Analysis of Leakage-Induced False Error Tolerant Error Detecting Latch for Sub/Near-Threshold Applications," in IEEE Transactions on Device and Materials Reliability, vol. 20, no. 2, pp. 366-375, June 2020, doi: 10.1109/TDMR.2020.2983210
J10. Priyamvada Sharma, Poorvi Jain and Bishnu Prasad Das, "An Optimal Device Sizing for a Performance-Driven and Area-Efficient Subthreshold Cell Library for IoT Applications" in Elsevier Microelectronics Journal, Volume 92, 2019, 104613.
J9. Poorvi Jain and Bishnu Prasad Das, "Reducing the Impact of Local Load Variation on the DUT in a Process Detector Using a Supply Controlled Ring Oscillator," in IEEE Transactions on Semiconductor Manufacturing, vol. 32, no. 4, pp. 605-612, Nov. 2019
J8. Poorvi Jain and Bishnu Prasad Das, "On-Chip Threshold Voltage Variability Estimation Using Reconfigurable Ring Oscillator," in IEEE Transactions on Semiconductor Manufacturing, vol. 32, no. 2, pp. 226-235, May 2019.
J7. Govinda Sannena and Bishnu Prasad Das, "Low Overhead Warning Flip-Flop Based on Charge Sharing for Timing Slack Monitoring," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 7, pp. 1223-1232, July 2018.
J6. Govinda Sannena and Bishnu Prasad Das, "Metastability immune and area efficient error masking flip-flop for timing error resilient designs", in Elsevier Integration, the VLSI Journal Vol. 61, Pages 101-113, March 2018.
J5. Bishnu Prasad Das and Hidetoshi Onodera, "Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 12, pp. 2535-2548, Dec. 2014
J4. Bishnu Prasad Das and Hidetoshi Onodera, "On-chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator," IEEE Transactions on Circuits and Systems II, Vol. 61, No. 3, pp. 183-187, Mar 2014.
J3. Bishnu Prasad Das and Hidetoshi Onodera, "Area-Efficient Reconfigurable-Array-Based Oscillator for Standard Cell Characterization," IET Circuits Devices Syst., Vol. 6, Iss. 6, pp. 429–436, Nov. 2012.
J2. Bishnu Prasad Das, Bharadwaj Amrutur, H.S.Jamadagni, N.V.Arvind, V. Visvanathan, "Voltage and Temperature Aware SSTA Using Neural Network Delay Model," IEEE Transactions on Semiconductor Manufacturing, vol. 24, No. 4, pp. 533- 544, Nov. 2011.
J1. Bishnu Prasad Das, Bharadwaj Amrutur, H.S.Jamadagni, N.V.Arvind, V. Visvanathan, "Within-Die Gate Delay Variability Measurement using Re-configurable Ring Oscillator," IEEE Transactions on Semiconductor Manufacturing, Vol. 22, No. 2, pp. 256-267, May 2009.
C38. Nithin Krishna M S and Bishnu Prasad Das, “ML-Based Prediction of Hybrid Hazard Resolution for a Pipelined RISC-V,” Accepted in IEEE ISVLSI 2026.
C37. Anu Verma , Sanskar Jain and Bishnu Prasad Das, “RISC-V Processor with Low-latency Configurable CORDIC-based Custom Instructions for Digital Signal Processing Applications,” Accepted in IEEE ISVLSI 2026.
C36. Anu Verma, Adabala Venugopal, Ritik Raj , Bishnu Prasad Das and Pramod Kumar Meher, “Instruction-based Dynamic Frequency Scaling for Enhancing Speed of RISC-V Processor in FPGA,” Accepted in IEEE ISVLSI 2026.
C35. Aranya Gupta*, Vishal Pal*, and Bishnu Prasad Das, “SecuBeat: A PUF and Secure Boot-Enabled Lightweight Authentication Framework for IoMT,” Accepted in IEEE ISVLSI 2026.
C34. Apurba Prasad Padhy and Bishnu Prasad Das “A Reconfigurable Dual-Mode FIR Architecture for Multichannel Single-Rate and Super-Sample-Rate Processing,” Accepted in IEEE ISVLSI 2026.
C33. Prajwal Sastry, Deenank Sharma, Sathvik Duddela, Adityavardhan Singh, Pranav Konidena, Bishnu Prasad Das, “An Ultra-Low Power Area Efficient Digital Decimation Filter using a Single Shift-Add block for a ∆Σ ADC,” Accepted in IEEE ISVLSI 2026.
C32. N. Dixit, S. Yadav, P. N. Singh and B. P. Das, "A Low Power High Resolution 2nd Order Current Mode Noise-Shaping SAR ADC with Scaled-Duty Cycle for Biomedical Applications," 2025 IEEE Biomedical Circuits and Systems Conference (BioCAS), Abu Dhabi, United Arab Emirates, 2025, pp. 507-511, doi: 10.1109/BioCAS67066.2025.00114.
C31. A. Verma and B. P. Das, "An Ultra-Low Jitter Divider-Less Phase-Locked Loop Using Differential Dual-Edge Sub-Sampling Phase Detector," 2025 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Busan, Korea, Republic of, 2025, pp. 1-5, doi: 10.1109/APCCAS67402.2025.11376831.
C30. F. Ahmad and B. P. Das, "Light-Weight Resilient Flip-flop for Error Detection and Same-cycle Correction in Pipelined Designs," 2025 IEEE 38th International System-on-Chip Conference (SOCC), Dubai, United Arab Emirates, 2025, pp. 1-6, doi: 10.1109/SOCC66126.2025.11235468.
C29. Sidharth Thomas, Jaskirat Singh Virdi, Anshul Verma, Bishnu Prasad Das, Kenichi Okada, and Pratap Narayan Singh, "A Peak-detector-based Ultra Low Power ECG ASIC for Early Detection of Cardio-Vascular Diseases,” IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, May 2024.
C28. Amandeep Singh and Bishnu Prasad Das, “PVT-Insensitive Time-Domain-based In-Memory Computation with Improved Linearity for Binary Neural Networks,” IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, May 2024.
C27. A. Verma and Bishnu Prasad Das, "A Low Power Dual-Band Sub-Sampling Phase Locked Loop with sub-100 fs RMS Jitter and <-255-dB FOMjitter," 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), Kolkata, India, 2024, pp. 156-161
C26. A. Singh and Bishnu Prasad Das, "Area-Efficient In-Memory Computation with Improved Linearity using Voltage-Controlled Delay Cell-based Ring Oscillator," 2023 IEEE International Symposium on Smart Electronic Systems (iSES), Ahmedabad, India, 2023, pp. 121-126
C25. Aditya Ramkumar, Anshul Verma and Bishnu Prasad Das, "Ultra-Low Power Non-Uniform SAR ADC based ECG detector for Early Detection of Cardiovascular Diseases," 2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID), Hyderabad, India, 2023, pp. 92-97.
C24. Apurba Prasad Padhy and Bishnu Prasad Das, "Lightweight Approximate Multiplier with Improved Accuracy in FPGA for Error Resilient Application," 2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID), Hyderabad, India, 2023, pp. 7-12.
C23. Anu Verma, Priyamvada Sharma, and Bishnu Prasad Das, "RISC-V Core with Approximate Multiplier for Error-Tolerant Applications," 25th Euromicro Conference on Digital System Design (DSD), Gran Canaria, Spain, Aug. 31th – Sept. 2nd, 2022.
C22. Aranya Gupta, Sanjeev Manhas, and Bishnu Prasad Das, "Highly Non-linear Feed-Forward Arbiter PUF against Machine Learning Attacks," 26th International Symposium on VLSI Design and Test (VDAT-2022), IIT Jammu, 17-19 July 2022.
C21. Anshul Verma and Bishnu Prasad Das, "Low Power Dual-Band Current Reuse-based LC-Voltage Controlled Oscillator with Shared Inductor for IoT Applications," 26th International Symposium on VLSI Design and Test (VDAT-2022), IIT Jammu, 17-19 July 2022. (Best Paper Award).
C20. Sumit Satyavijay Wadkar, Bishnu Prasad Das and Pramod Kumar Meher, "Low Latency Scaling-Free Pipeline CORDIC Architecture Using Augmented Taylor Series," 2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), Rourkela, India, 2019, pp. 312-315.
C19. Prasanna Kumar Saragada, Meghnath Rathod and Bishnu Prasad Das, "An In-Memory Architecture for Machine Learning Classifier Using Logistic Regression," 2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), Rourkela, India, 2019, pp. 209-214.
C18. Priyamvada Sharma and Bishnu Prasad Das, "A True Single-Phase Error Masking Flip-Flop with Reduced Clock Power for Near-Threshold Designs," 23rd International Symposium on VLSI Design and Test (VDAT-2019), Indore, India. (Best Regular Paper Award (II prize)).
C17. Poorvi Jain and Bishnu Prasad Das, "On-Chip Threshold Voltage Variability Detector Targeting Supply of Ring Oscillator for Characterizing Local Device Mismatch," IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS), Kita-Kyushu City, Fukuoka, Japan, 2019, pp. 120-125.
C16. Swaati and Bishnu Prasad Das, " A 10T Subthreshold SRAM Cell with Minimal Bitline Switching for Ultra-low Power Applications", 21st International Symposium on VLSI Design and Test (VDAT), 2017, Roorkee, India.
C15. Poorvi Jain and Bishnu Prasad Das, "Within-Die Threshold Voltage Variability Estimation Using Reconfigurable Ring Oscillator", IEEE VLSI Design conference, 2017, Hyderabad, India.
C14. Govinda Sannena and Bishnu Prasad Das, "Area and Power-efficient Timing Error Predictor for Dynamic Voltage and Frequency Scaling Application," IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), December 19-21, 2016, Gwalior, India
C13. Govinda Sannena and Bishnu Prasad Das, "A Metastability Immune Timing Error Masking FlipFlop for Dynamic Variation Tolerance," ACM GLSVLSI, Boston, USA, May, 2016.
C12. Kaushik Vaidyanathan, Bishnu P Das and Larry Pileggi, "Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack," IEEE/ACM Design Automation Conference (DAC), June, 2014
C11. Kaushik Vaidyanathan, Bishnu P Das, Ekin Sumbul, Renzhi Liu, Larry Pileggi, "Building trusted ICs using split fabrication," IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2014
C10. Bishnu Prasad Das and Hidetoshi Onodera, "Reconfigurable Array-Based Area-Efficient Test Structure for Standard Cell Characterization," IEEE Twelfth Workshop on RTL and High Level Testing, 2011.
C9. Bishnu Prasad Das and Hidetoshi Onodera, "Warning Prediction Sequential for Transient Error Prevention," IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2010.
C8. Bishnu Prasad Das and Hidetoshi Onodera, "Accurate Individual Gate Delay Measurement to Study Within-die Variations", IEICE Spring meeting, Sendai, Japan, March 2010
C7. Bishnu Prasad Das, "Delay Variability: Modeling and On-chip Measurement", PhD Forum, Design Automation & Test in Europe, Nice, France, April, 2009
C6. Bishnu Prasad Das, Bharadwaj Amrutur, H.S.Jamadagni, N.V.Arvind, V. Visvanathan, "Within-Die Gate Delay Variability Measurement using Re-configurable Ring Oscillator", IEEE Custom Integrated Circuits Conference (CICC), San Jose, USA, September 2008.
C5. Bishnu Prasad Das, Janakiraman V, B Amrutur, H.S. Jamadagni, N.V. Arvind, "Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations", IEEE VLSI Design Conference, Hyderabad, India, Jan 2008
C4. Janakiraman V, Bishnu Prasad Das, B Amrutur, "Voltage and temperature scalable standard cell leakage models based on stacks for statistical leakage characterization", IEEE VLSI Design Conference, Hyderabad, India, Jan 2008.
C3. Bishnu Prasad Das, Bharadwaj Amrutur, H S Jamadagni "Voltage scalable statistical gate delay models using neural networks", 11th IEEE VLSI Design And Test Symposium, Kolkota, India, 2007.
C2. Janakiraman, Bishnu Prasad Das, Vish Visvanathan and B. Amrutur, "Leakage modeling of logic gates considering effect of input vectors", 11th IEEE VLSI Design And Test Symposium, Kolkota, India, 2007
C1. Bishnu Prasad Das, Bharadwaj Amrutur, H.S.Jamadagni, "Critical Path Modeling for Dynamic Voltage Scaling (DVS) in Low Power Applications", 10th IEEE VLSI Design and Test Symposium, Goa, India, 2006.
